View ACS8527_4362054.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Line Card Protection Switch for PDH, SONET or SDH Systems ADVANCED COMMUNICATIONS Description FINAL Features DATASHEET
ACS8527 MUXPLL
The ACS8527 is a highly integrated, single-chip, MUX with PLL solution for protection switching between two SECs (SDH/SONET Equipment Clocks) from Master and Slave SETS (Synchronous Equipment Timing Source) clock cards, for line cards in a PDH, SONET or SDH Network Element. The ACS8527 has fast activity monitors on the inputs and will raise a flag on a pin if there is a loss of activity on the currently selected input. The protection switching between the input reference clock sources is controlled by an external pin. The ACS8527 has two SEC reference clock input ports, configured for expected frequency by setting hardware pins. The ACS8527 can perform frequency translation, converting, for example, an 8 kHz SEC input clock from a backplane into a 155.52 MHz clock for local line cards. The ACS8527 generates two independent SEC clock outputs, one on a LVDS port and one on a TTL/CMOS port, at spot frequencies configured by hardware pins. The spot frequencies range from 1.544 MHz up to 155.52 MHz. The ACS8527 also provides an 8 kHz Frame Sync output and 2 kHz Multi-Frame Sync output.
Line card protection switch - partners Semtech SETS devices for Stratum 3E/3/4E/4 PDH, SONET or SDH applications High performance DPLL/APLL solution Output jitter compliant to STM-1 Two independent SEC inputs ports (TTL) Four independent output ports: Two clock ports: one LVDS, one TTL Two Syncs (TTL): 8 kHz FrSync & 2 KHz MFrSync I/O frequencies configurable via hardware pins: TTL I/O ports: spot frequencies 1.544 MHz to 77.76 MHz LVDS output port: spot frequencies 19.44 MHz to 155.52 MHz Digital Holdover mode on input failure "Loss of activity" on selected input flagged on dedicated pin Source switch under external hardware control 7O Hz (acquisition) /35 Hz (locked) DPLL bandwidth Output clock phase continuity to GR-1244-CORE[13] Single 3.3 V operation, 5 V I/O compatible IEEE 1149.1 JTAG Boundary Scan is supported Operating temperature (ambient) of -40 to +85C Available in LQFP 64 package Lead (Pb)-free version available (ACS8527T). RoHS and WEE compliant
Block Diagram
Figure 1 Block Diagram of the ACS8527 MUXPLL
IP_FREQ SONSDHB SRCSW 2 x SEC TTL inputs SEC1 SEC Inputs: Input Frequencies 8kHz 1.544 MHz SEC2 2.048 MHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz TCK 77.76 MHz TDI TMS TRST TDO Input SEC Port Selector
LOS_ALARM SEC Outputs: 01 (LVDS) Output Port Frequency Selection 02 (TTL)
DPLL
APLL
Sync Outputs: MFrSync 2 kHz (TTL) FrSync 8 kHz (TTL) Output Frequencies/MHz 01 Output: 02 Output: 19.44 1.544 25.92 2.048 34.368 (E3) 3.088 38.88 19.44 44.736 (DS3) 25.92 51.84 34.368 (E3) 77.76 38.88 155.52 44.736 (DS3) 51.84 77.76
F8527D_001BLOCKDIA_01
IEEE 1149.1 JTAG
Chip Clock Generator
TCXO or XO
OP_FREQ1 OP_FREQ2
Revision 4.01/June 2006 (c) Semtech Corp.
Page 1
www.semtech.com
Table of Contents ADVANCED COMMUNICATIONS Table of Contents
Section
ACS8527 MUXPLL
DATASHEET
Page
FINAL
Description ................................................................................................................................................................................................. 1 Block Diagram............................................................................................................................................................................................ 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 3 Pin Description........................................................................................................................................................................................... 4 Introduction................................................................................................................................................................................................ 6 General Description................................................................................................................................................................................... 6 Inputs ..................................................................................................................................................................................................6 Preconfiguring Inputs - Expected Input Frequency ................................................................................................................ 6 Preconfiguring Inputs - SONET/SDH ....................................................................................................................................... 7 Selection of Input SECs .....................................................................................................................................................................7 Initialization .............................................................................................................................................................................. 7 SEC Selection - SRCSW pin...................................................................................................................................................... 7 Output Clock Phase Continuity on Source Switchover .......................................................................................................... 7 Phase Locked Loops (PLLs) ..............................................................................................................................................................7 DPLL Acquisition Bandwidth.................................................................................................................................................... 8 DPLL Input Tracking (Locked) Bandwidth............................................................................................................................... 8 DPLL Damping Factor .............................................................................................................................................................. 8 Fast Activity Monitor................................................................................................................................................................. 8 Outputs ...............................................................................................................................................................................................8 Output Frequency Selection .................................................................................................................................................... 8 Local Oscillator Clock.........................................................................................................................................................................9 Power-On Reset..................................................................................................................................................................................9 Status Reporting ................................................................................................................................................................................9 Electrical Specifications ......................................................................................................................................................................... 10 JTAG ................................................................................................................................................................................................. 10 Over-voltage Protection .................................................................................................................................................................. 10 ESD Protection ................................................................................................................................................................................ 10 Latchup Protection.......................................................................................................................................................................... 10 Maximum Ratings ........................................................................................................................................................................... 11 Operating Conditions ...................................................................................................................................................................... 11 DC Characteristics .......................................................................................................................................................................... 11 Jitter Performance .......................................................................................................................................................................... 13 Input/Output Timing ....................................................................................................................................................................... 15 Package Information .............................................................................................................................................................................. 16 Thermal Conditions......................................................................................................................................................................... 17 Application Information .......................................................................................................................................................................... 18 References .............................................................................................................................................................................................. 19 Abbreviations .......................................................................................................................................................................................... 19 Notes ....................................................................................................................................................................................................... 20 Trademark Acknowledgements ............................................................................................................................................................. 20 Revision Status/History ......................................................................................................................................................................... 21 Ordering Information .............................................................................................................................................................................. 22 Disclaimers...................................................................................................................................................................................... 22 Contacts........................................................................................................................................................................................... 22
Revision 4.01/June 2006 (c) Semtech Corp.
Page 2
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Pin Diagram
Figure 2 ACS8527 Pin Diagram
FINAL
DATASHEET
1 2 3 4 5 6 7 8 9 10 1 11 12 13 14 15 16
AGND1 IC1 AGND2 VA1+ LOS_ALARM REFCLK DGND1 VD1+ VD2+ DGND2 DGND3 VD3+ SRCSW VA2+ AGND3 IC2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SONSDHB O1_FREQ2 IC13 IC12 IC11 NC3 AGND4 VA3+ O2 NC2 VDD3 DGND6 IC10 TDI TDO TCK
ACS8527 MUXPLL
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PORB IC9 O1_FREQ1 O1_FREQ0 NC1 IC8 IC7 TMS DGND5 VDD2 O2_FREQ1 TRST O2_FREQ2 O2_FREQ0 IP_FREQ2 IP_FREQ1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
FrSync MFrSync O1POS O1NEG GND_DIFF VDD_DIFF IC3 IC4 IC5 IC6 VDD5V IP_FREQ0 SEC1 SEC2 DGND4 VDD1
F8527D_002PINDIAG_01
Revision 4.01/June 2006 (c) Semtech Corp.
Page 3
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Pin Description
Table 1 Power Pins
Pin Number 8, 9, 12 22 27 Symbol VD1+, VD2+, VD3+ VDD_DIFF VDD5V I/O P P P Type Description Supply Voltage: Digital supply to gates in analog section, +3.3 Volts 10%. Supply Voltage: Digital supply for differential output pins 19 and 20, +3.3 Volts 10%. Digital Supply for +5 Volts tolerance to input pins. Connect to +5 Volts (10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts. Supply Voltage: Digital supply to logic, +3.3 Volts 10%. Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts 10%. Supply Voltage: Analog supply to output PLLs APLL2 and APLL1, +3.3 Volts 10%. Supply Ground: Analog ground for output PLLs APLL2 and APLL1. P P P P Supply Ground: Digital ground for components in PLLs. Supply Ground: Digital ground for logic. Supply Ground: Digital ground for differential output pins 19 and 20. Supply Ground: Analog grounds.
FINAL
DATASHEET
32, 39, 54 4 14, 57 15, 58 7, 10, 11 31, 40, 53 21 1, 3
VDD1, VDD2, VDD3, VA1+ VA2+, VA3+ AGND3, AGND4 DGND1, DGND2, DGND3 DGND4, DGND5, DGND6 GND_DIFF AGND1, AGND2
P P P
-
Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor.
Table 2 Internally Connected
Pin Number 2, 16, 23, 24, 25, 26, 42, 43, 47, 52, 60, 61, 62 44, 55, 59 Symbol IC1, IC2, IC3, IC4, IC5, IC6, IC7, IC8, IC9, IC10, IC11, IC12, IC13 NC1, NC2, NC3 I/O Type Description Internally Connected: Leave to float.
-
-
Not Connected: Leave to float
Revision 4.01/June 2006 (c) Semtech Corp.
Page 4
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS
Table 3 Other Pins
Pin Number 5 6 13 Symbol LOS_ALARM REFCLK SRCSW I/O O I I Type TTL/CMOS TTL TTLD Description Loss Of Signal Alarm: Flag to indicate loss of activity of currently selected reference source is raised on this pin. Reference Clock: 12.800 MHz (refer to section headed Local Oscillator Clock). Source Switching: Controls switchover between SEC1 and SEC2 inputs as the selected reference. SRCSW must be held High on power-up or reset, and for a further 251 ms after PORB has gone High. See "Initialization" on page 7. Output Reference: 8 kHz Frame Sync output. Output Reference: 2 kHz Multi-Frame Sync output. Output Reference 1: Differential output. LVDS. Input Reference Frequency Select: Frequency select for input SEC1 and SEC2. Input Reference 1: Primary input. Input Reference 2: Secondary input. Input Reference Frequency Select: Frequency select for input SEC1 and SEC2. Input Reference Frequency Select: Frequency select for input SEC1 and SEC2. Output O2 Frequency Select: Frequency select for output O2. Output O2 Frequency Select: Frequency select for output O2. JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for normal device operation (JTAG logic transparent). NC if not used. Output O2 Frequency Select: Frequency select for output O2. JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. NC if not used. Output O1 Frequency Select: Frequency select for output O1. Output O1 Frequency Select: Frequency select for output O1. Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. JTAG Clock: Boundary Scan clock input. JTAG Output: Serial test data output. Updated on falling edge of TCK. JTAG Input: Serial test data Input. Sampled on rising edge of TCK. NC if not used. Output Reference: Programmable, default 19.44 MHz. Output O1 Frequency Select: Frequency select for output O1. SONET or SDH frequency select: Sets the device for SONET or SDH frequencies on power-up/reset.
FINAL
DATASHEET
17 18 19, 20 28 29 30 33 34 35 36 37 38 41 45 46 48 49 50 51 56 63 64
FrSync MFrSync O1POS, O1NEG IP_FREQ0 SEC1 SEC2 IP_FREQ1 IP_FREQ2 O2_FREQ0 O2_FREQ2 TRST O2_FREQ1 TMS O1_FREQ0 O1_FREQ1 PORB TCK TDO TDI O2 O1_FREQ2 SONSDHB
O O O I I I I I I I I I I I I I I O I O I I
TTL/CMOS TTL/CMOS LVDS TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLD TTLU TTLU TTLU TTLD TTL/CMOS TTLD TTL/CMOS TTLU TTLD
Revision 4.01/June 2006 (c) Semtech Corp.
Page 5
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Introduction FINAL DATASHEET
initial lock (with no input reference) or in Digital Holdover, the frequency stability is only determined by the stability of the external oscillator module. This gives the key advantage of confining all temperature critical components to one well defined and pre-calibrated oscillator module, whose performance can be chosen to match the application. An Evaluation board is available for device introduction. This has its own documentation "ACS8527-EVB".
The ACS8527 is a highly integrated, single-chip solution for protection switching of two SEC inputs from, for example, Master and Slave SETS clock cards sources, for Line Cards in a SONET or SDH Network Element. The ACS8527 has fast activity monitors on the SEC clock inputs. The ACS8527 is a standalone part where all input and output frequencies are set by external control using the IP_FREQ, OP_FREQ and SONSDHB pins. The SRCSW pin is used to select one of the two SEC inputs to lock to. The SRCSW pin must remain High for an initialization period of at least 251 ms following power-up or reset (251 ms after the PORB signal has gone High). SRCSW Low immediately after a power-up or reset is not supported. The ACS8527 has two SEC inputs from which it can generate independent clocks on outputs 01 and 02 (11 possible output clock frequencies). In addition, there are two Sync outputs; 8 kHz Frame Synchronization (FrSync) signal and a 2 kHz Multi-Frame Synchronization (MFrSync) signal. Initially the ACS8527 generates a stable, low-noise clock signal at a frequency to the same accuracy as the external oscillator. The device always attempts to lock to one of its inputs (according to the value on the SRCSW pin). Once locked to a reference the accuracy of the output clock is determined directly by the accuracy of the input reference. In the absence of any input references the device simply maintains its most recent frequency in a Digital Holdover mode. However, as soon as the DPLL (Digital Phase Locked Loop) detects an input presence, it will attempt to lock to it and will not "qualify" it first. As soon as the DPLL detects a failure on the input, the DPLL freezes its operating frequency and raises the LOS alarm on device pin LOS_ALARM. The overall PLL (Phased Locked Loop) loop bandwidth, damping, pull-in range and frequency accuracy are all determined by fixed digital parameters that provide a consistent level of performance. An Analog PLL (APLL) takes the signal from the DPLL output and provides a lower jitter output. The APLL bandwidth is set four orders of magnitude higher than the DPLL bandwidth. This ensures that the overall system performance still maintains the advantage of consistent behavior provided by the digital approach. The DPLLs are clocked by the external oscillator module (TCXO or XO) so that prior to
Revision 4.01/June 2006 (c) Semtech Corp.
General Description
The following description refers to the Block Diagram (Figure 1 on page 1).
Inputs
The ACS8527 SETS device has two TTL/CMOS compatible SEC input ports. They are 3 V and 5 V compatible (with clamping if required by connecting the VDD5V pin). Refer to the "Electrical Specifications" on page 10 for more information on electrical compatibility. Input frequencies supported range from 8 kHz to 77.76 MHz. Common E1, DS1, OC-3 and sub-divisions are supported as spot frequencies that the DPLLs will directly lock to. In addition to the SEC inputs, there are four configuration pins IP_FREQ [2:0] and SONSDHB used to configure the input to expect a particular input frequency (same value applies to both inputs), and a control pin SRCSW for switching between SEC1 and SEC2 as the selected input reference to which the device tries to lock.
Preconfiguring Inputs - Expected Input Frequency
The inputs SEC1 and SEC2 must be preconfigured to expect a particular input frequency. This can be selected from a range of spot frequencies by configuring the hardware pins IP_FREQ [2:0] and SONSDHB, which are read on reset. The combined pin states of IP_FREQ [2:0] and SONSDHB represent a 4-bit word which addresses a particular frequency value as given in Table 4. The frequency selected by the hardware configuration is always applied to both inputs on Power-up or Reset, so both will be preconfigured to expect the same frequency.
www.semtech.com
Page 6
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS FINAL DATASHEET
Table 4 Hardware Configuration for Selecting Expected Input Frequency on SEC1 and SEC2
IP_FREQ Pins 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 SONSDHB Pin X 0 1 X X X X X X Input frequency
After initialization, the output clocks are stable and the device will operate as a simple switch, with the DPLL trying to lock on to the selected reference source.
8 kHz 2.048 MHz 1.544 MHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz
Output Clock Phase Continuity on Source Switchover
A phase offset between SEC inputs will be seen as a phase shift on the output on source switchover equal to the input phase offset. (Note...The ACS8527 has no Phase Build-out function to accommodate this. If this function is required, it is available on the AS8525 LC/P device). The rate of change of phase on the output, during the time between input switchover and the output settling to a steady state, is dependent on input frequency, and input phase change. The ACS8527 always complies with GR-1244-CORE[13] spec for Stratum 3 (max rate of phase change of 81ns/1.326 ms), for input frequencies at 6.48 MHz or higher. For inputs at a lower frequency than 6.48 MHz (e.g. 8 kHz), then to ensure compliance with GR-1244-CORE[13], the input phase difference between the Master and Slave inputs to the line card PLL should be limited to less than 190 ns. A well designed system would have master and slave clock from the clock sync cards aligned to within a few nanoseconds. In which case a complete system using the Semtech SETS clock card parts (ACS8530, ACS8520 or ACS8510) and this line card part would be fully compliant to GR-1244-CORE[13] specifications under all conditions due to the lower frequency range and bandwidth set at the clock card end.
Preconfiguring Inputs - SONET/SDH
The SONSDHB pin is used to select SDH or SONET mode for the entire device and its setting affects parameters other than just the expected input frequency selection, e.g. output frequency. To set the device for use in a SONET network, set SONSDHB high. For SDH, set SONSDHB low.
Selection of Input SECs
Initialization
Switching between inputs SEC1 and SEC2 is triggered directly from a dedicated pin (SRCSW), though for the device to operate properly, the device must first be initialized by holding the pin High during reset and for at least a further 251 ms after PORB has gone High (250 ms allowance for the internal reset to be removed plus 1 ms allowance for APLLs to start-up and become stable). If SCRSW is held Low at any time during the 251 ms initialization period, this will result in incorrect device operation. A simple external circuit to set SCRSW high for the required period is shown in the "Simplified Application Schematic" on page 18.
Phase Locked Loops (PLLs)
The PLL circuitry (See Figure 1) is represented by a DPLL and an output multiplying and filtering APLL. The device is more complex than the representation suggests, with several DPLLs and APLLs being used in different configurations to provide a range of frequencies at the outputs, with the internal configuration optimizing for jitter filtering and wander tracking. The output frequencies available are shown in Table 6. The DPLL initially tries to lock to the input frequency of the selected input SEC. It uses a wide "acquisition" bandwidth setting until it has achieved frequency lock, then the DPLL switches to using a narrower "tracking" (locked) bandwidth setting as it locks to the phase of the input.
www.semtech.com
SEC Selection - SRCSW pin
After the ACS8527 has been initialized (see previous "Initialization" section), then the value of SRCSW pin directly selects either SEC1 (SRCSW High) or SEC2 (SRCSW Low). The frequency tolerance of SEC1 and SEC2 is 80 ppm with respect to the local oscillator clock.
Revision 4.01/June 2006 (c) Semtech Corp.
Page 7
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS
DPLL Acquisition Bandwidth
The ACS8527 DPLL has a preset acquisition bandwidth of 70 Hz.
FINAL
DATASHEET
the input becomes active again then the DPLL will continue to lock to the input, with little disturbance.
DPLL Input Tracking (Locked) Bandwidth
The ACS8527 DPPL has a preset tracking bandwidth of 35 Hz. This bandwidth setting corresponds to the -3 dB jitter attenuation point on the ACS8527's jitter transfer characteristic.
Outputs
The ACS8527 delivers four output signals on the following ports: Two clocks, one each on outputs O1 and O2, and two Sync signals, one each on output ports FrSync and MFrSync. Outputs O1 and O2 are independent of each other and are individually selectable. Output 01 is an LVDS compatible differential port (pins O1POS and O1NEG). Output O2 (pin O2) and the Sync outputs are TTL/CMOS compatible. The two Sync outputs, FrSync (8 kHz) and MFrSync (2 kHz), are derived from the DPLL.
DPLL Damping Factor
The DPLL damping factor is 10, giving a PLL jitter transfer peak gain of 0.06 dB.
Fast Activity Monitor
Anomalies on the selected clock have to be detected as they occur and the PLL must be temporarily isolated until the clock is once again pure. The phase locked loop itself contains a fast activity monitor such that within approximately two missing input clock cycles, the LOS alarm on pin LOS_ALARM is raised and the DPLL is frozen in Digital Holdover mode. With the DPLL in Digital Holdover mode it is isolated from further disturbances. If
Output Frequency Selection
The frequencies available on the outputs can be selected from a range of spot frequencies by hardware selection, configuring the pins OP_FREQ1 [2:0], OP_FREQ2[2:0] and SONSDH, which are read on reset. Tables 5 and 6 show the hardware settings for selecting from 11 output frequencies on outputs 01 and 02.
Table 5 Output 01 Frequency Selection by Hardware Configuration
O1_FREQ 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 X 0 1 X X X X X X SONSDHB Pin Output Frequency/ MHz 0 34.368 44.736 19.44 25.92 38.88 51.84 77.76 155.52 Jitter Level (typ) rms (ps) 120 110 60 60 60 60 60 60 p-p (ns) 1 1 0.6 0.6 0.6 0.6 0.6 0.6
Revision 4.01/June 2006 (c) Semtech Corp.
Page 8
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS
O2_FREQ 2 0 0 1 0 0 0 0 1 X 0 1 0 1 0 1 X X X X X
FINAL
SONSDHB Pin O1_FREQ = ``001'' X FALSE Output Frequency/ MHz 0 2.048 1.544 2.048 3.088 34.368 44.736 19.44 25.92 38.88 51.84 77.76
DATASHEET
Jitter Level (typ) rms (ps) 400 200 900 110 120 110 60 60 60 60 60 p-p (ns) 2 1.2 0.45 0.75 1 1 0.6 0.6 0.6 0.6 0.6
Table 6 Output 02 Frequency Selection by Hardware Configuration
0
0
1
TRUE X X X X X X X
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
Local Oscillator Clock
The Master system clock on the ACS8527 should be provided by an external clock oscillator of frequency 12.800 MHz. Wander on the local oscillator clock will not have a significant effect on the output clock whilst in Locked mode. Prior to initial lock or in Digital Holdover mode, wander on the crystal is more significant. Variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. These effects must be limited by careful selection of a suitable component for the local oscillator. Please contact Semtech for information on crystal oscillator suppliers.
may be re-asserted at any time to restore defaults. This is implemented simply using an external capacitor to GND along with the internal pull-up resistor. The ACS8527 holds itself in a reset state for 250 ms after the PORB pin has been pulled High. In normal operation PORB should be held High.
Status Reporting
In the event of loss of SEC input signal, LOS flag is raised on the LOS_ALARM pin. The LOS alarm is active low, and high impedance when inactive, i.e. when an LOS alarm exists, the output will be driven low; with no LOS alarm, the output will float. This is designed to be able to be connected to a processor together with other interrupt sources to trigger an interrupt. The output will require a pull-up resistor to pull the voltage up when the alarm is inactive.
Power-On Reset
The Power-On Reset (PORB) pin resets the device if forced Low. The reset is asynchronous, the minimum Low pulse width is 5 ns. Reset must be asserted at power on, and
Revision 4.01/June 2006 (c) Semtech Corp.
Page 9
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Electrical Specifications JTAG
The JTAG connections on the ACS8527 allow a full boundary scan to be made. The JTAG implementation is fully compliant to IEEE 1149.1[4], with the following minor exceptions, and the user should refer to the standard for further information. 1. The output boundary scan cells do not capture data from the core, and so do not support INTEST. However this does not affect board testing. 2. In common with some other manufacturers, pin TRST is internally pulled Low to disable JTAG by default. The standard is to pull High. The polarity of TRST is as the standard: TRST High to enable JTAG boundary scan mode, TRST Low for normal operation. The JTAG timing diagram is shown in Figure 3.
FINAL Over-voltage Protection
DATASHEET
The ACS8527 may require Over-voltage Protection on input reference clock ports according to ITU recommendation K.41[10]. Semtech protection devices are recommended for this purpose (see Protection section on Semtech website: http://www.semtech.com.
ESD Protection
Suitable precautions should be taken to protect against electrostatic damage during handling and assembly. This device incorporates ESD protection structures that protect the device against ESD damage at ESD input levels up to at least +/2kV using the Human Body Model (HBD) MIL-STD-883D Method 3015.7, for all pins.
Latchup Protection
This device is protected against latchup for input current pulses of magnitude up to at least 100 mA to JEDEC Standard No. 78 August 1997.
Figure 3 JTAG Timing
tCYC TCK tSUR TMS TDI tDOD TDO
F8110D_022JTAGTiming_01
tHT
Table 7 JTAG Timing (for use with Figure 3)
Parameter Cycle Time TMS/TDI to TCK rising edge time TCK rising to TMS/TDI hold time TCK falling to TDO valid Symbol tCYC tSUR tHT tDOD Minimum 50 3 23 Typical Maximum 5 Units ns ns ns ns
Revision 4.01/June 2006 (c) Semtech Corp.
Page 10
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Maximum Ratings FINAL DATASHEET
Important Note: The Absolute Maximum Ratings, Table 8, are stress ratings only, and functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 8 Absolute Maximum Ratings
Parameter Supply Voltage VDD1, VDD2, VDD3, VD1+,VD2+, VD3+, VA1+, VA2+, VA3+, VDD_DIFF Input Voltage (non-supply pins) Output Voltage (non-supply pins) Ambient Operating Temperature Range Storage Temperature Symbol VDD Minimum -0.5 Maximum 3.6 Units V
VIN VOUT TA TSTOR
-40 -50
5.5 5.5 +85 +150
V V
oC oC
Operating Conditions
Table 9 Operating Conditions
Parameter Power Supply (dc voltage) VDD1, VDD2, VDD3, VD1+,VD2+, VD3+, VA1+, VA2+, VA3+, VDD_DIFF Power Supply (dc voltage) VDD5V Ambient Temperature Range Supply Current (Typical - one 19 MHz output) Total Power Dissipation Symbol VDD Minimum 3.0 Typical 3.3 Maximum 3.6 Units V
VDD5V TA IDD PTOT
3.0 -40 -
3.3/5.0 110 360
5.5 +85 200 720
V
o
C
mA mW
DC Characteristics
Table 10 DC Characteristics: TTL Input Port
Across all operating conditions, unless otherwise stated PARAMETER VIN High VIN Low Input Current Symbol VIH VIL IIN Minimum 2 Typical Maximum 0.8 10 Units V V A
Revision 4.01/June 2006 (c) Semtech Corp.
Page 11
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS
Across all operating conditions, unless otherwise stated Parameter VIN High VIN Low Pull-up Resistor Input Current Symbol VIH VIL PU IIN Minimum 2 25 Typical Maximum 0.8 95 120 Units V V k
FINAL
DATASHEET
Table 11 DC Characteristics: TTL Input Port with Internal Pull-up
Table 12 DC Characteristics: TTL Input Port with Internal Pull-down
Across all operating conditions, unless otherwise stated Parameter VIN High VIN Low Pull-down Resistor (except TCK input) Pull-down Resistor (TCK input only) Input Current Symbol VIH VIL PD PD IIN Minimum 2 25 12.5 Typical Maximum 0.8 95 47.5 120 Units V V k k A
Table 13 DC Characteristics: TTL Output Port
Across all operating conditions, unless otherwise stated Parameter VOUT Low (lOL = 4 mA) VOUT High (lOH = 4 mA) Drive Current Symbol VOL VOH ID Minimum 0 2.4 Typical Maximum 0.4 4 Units V V mA
Table 14 DC Characteristics: LVDS Output Port
Across all operating conditions, unless otherwise stated Parameter LVDS Output High Voltage (Note (i)) LVDS Output Low Voltage (Note (i)) LVDS Differential Output Voltage Symbol VOHLVDS VOLLVDS VODLVDS Minimum 0.885 250 Typical Maximum 1.585 450 Units V V mV
Revision 4.01/June 2006 (c) Semtech Corp.
Page 12
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS
Across all operating conditions, unless otherwise stated Parameter LVDS Change in Magnitude of Differential Output Voltage for complementary States (Note (i)) LVDS Output Offset Voltage Temperature = 25oC (Note (i)) Symbol VDOSLVDS Minimum Typical Maximum 25 Units mV
FINAL
DATASHEET
Table 14 DC Characteristics: LVDS Output Port (cont...)
VOSLVDS
1.125
-
1.275
V
Notes: (i) With 100 load between the differential outputs.
Figure 4 Recommended Line Termination for LVDS Output Port
ZO = 50
O1POS 100 01NEG Fully Programmable Output Frequencies
ZO = 50
F8522D_025LVDS_02
Jitter Performance
Output jitter generation measured over 60 second interval, UI p-p max measured using C-MAC E2747 12.8 MHz TCXO on ICT Flexacom tester. Table 15 Output Jitter Generation at 35 Hz Bandwidth and 8 kHz Input
Test Definition Specification G813[8] for 155 MHz o/p option 1 G813
[8]
Jitter Spec Filter 65 kHz - 1.3 MHz 20 Hz - 100 kHz 12 kHz - 1.3 MHz 10 Hz - 40 kHz 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz 20 Hz - 100 kHz 49 Hz - 100 kHz 20 Hz - 100 kHz 0.1 p-p 0.05 p-p 0.1 p-p 0.05 p-p 0.5 p-p 0.075 p-p 0.5 p-p 0.2 p-p 0.05 p-p UI
ACS8527 Jitter UI (TYP) 0.073 p-p 0.012 p-p 0.069 p-p 0.011 p-p 0.083 p-p 0.073p-p 0.012 p-p 0.012 p-p 0.012 p-p
& G812
[7]
for 2.048 MHz option 1
G813[8] for 155 MHz o/p option 2 G812[7] for 1.544 MHz o/p G812[7] for 155 MHz electrical G812[7] for 155 MHz electrical
ETS-300-462-3[2] for 2.048 MHz SEC o/p ETS-300-462-3[2] for 2.048 MHz SEC o/p ETS-300-462-3[2] for 2.048 MHz SSU o/p
Revision 4.01/June 2006 (c) Semtech Corp.
Page 13
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS
Test Definition Specification ETS-300-462-5[3] for 155 MHz o/p ETS-300-462-5[3] for 155 MHz o/p GR-253-CORE[11] net i/f, 51.84 MHz o/p GR-253-CORE[11] net i/f, 51.84 MHz o/p GR-253-CORE[11] net i/f, 155 MHz o/p Filter 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz 100 Hz - 0.4 MHz 20 kHz to 0.4 MHz 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz 12 kHz - 1.3 MHz 0.5 p-p 0.1 p-p 1.5 p-p 0.15 p-p 1.5 p-p 0.15 p-p 0.1 p-p 0.01 rms GR-253-CORE[11] cat II elect i/f, 51.84 MHz 12 kHz - 400 kHz 0.1 p-p 0.01 rms GR-253-CORE[11] DS1 i/f, 1.544 MHz 10 Hz - 40 kHz 0.1 p-p 0.01 rms AT&T 62411[1] for 1.544 MHz AT&T 62411[1] for 1.544 MHz AT&T 62411[1] for 1.544 MHz AT&T 62411[1] for 1.544 MHz G-742[6] for 2.048 MHz 10 Hz - 8 kHz 8 Hz - 40 kHz 10 Hz - 40 kHz Broadband DC - 100 kHz 18 kHz - 100 kHz 20 Hz - 100 kHz 10 Hz - 40kHz 8 kHz - 40kHz > 10 Hz 0.02 rms 0.025 rms 0.025 rms 0.05 rms 0.25 rms 0.05 p-p 0.05 p-p 5.0 p-p 0.1 p-p 0.05 p-p
FINAL
Jitter Spec UI
DATASHEET
ACS8527 Jitter UI (TYP) 0.083 p-p 0.073 p-p 0.038 p-p 0.019 p-p 0.083 p-p 0.073 p-p 0.069 p-p 0.009 rms 0.008 p-p 0.004 rms 0.0046 p-p <0.001 rms <0.001 rms <0.001 rms <0.001 rms <0.001 rms 0.012 rms 0.012 p-p 0.012 p-p 0.001 p-p 0.001 p-p 0.001 p-p
Table 15 Output Jitter Generation at 35 Hz Bandwidth and 8 kHz Input (cont...)
GR-253-CORE[11] net i/f, 155 MHz o/p GR-253-CORE[11] cat II elect i/f, 155 MHz
G-742[6] for 2.048 MHz G-736[5] for 2.048 MHz GR-499-CORE[12] & G824[9] for 1.544 MHz GR-499-CORE
[12]
& G824
[9]
for 1.544 MHz
GR-1244-CORE[13] for 1.544 MHz
Note...This table is only for comparing the ACS8527 output jitter performance against values and quoted in various specifications for given conditions. It should not be used to infer compliance to any other aspects of these specifications.
Revision 4.01/June 2006 (c) Semtech Corp.
Page 14
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Input/Output Timing
Figure 5 Input/Output Timing (Typical Conditions)
FINAL
DATASHEET
Input/Output
8 kHz input
Delay
Output
MFrSync (2 kHz)
Min/Max Phase Alignment (FrSync Alignment switched on)
+8.2 1.5 ns 8 kHz output FrSync (8 kHz) 19.44 MHz input +4.3 1.5 ns 19.44 MHz output DS1 (1.544 MHz) -1.2 1.25 ns -1.2 0.5 ns
25.92 MHz input +4.7 1.5 ns 25.92 MHz output
E1 (2.048 MHz)
-1.2 1.25 ns
DS3 (44.736 MHz) 38.88 MHz input +4.6 1.5 ns 38.88 MHz output E3 (34.368 MHz)
-3.75 1.25 ns
-3.75 1.25 ns
51.84 MHz input +3.0 1.5 ns 51.84 MHz output
19.44 MHz
-3.75 1.25 ns
25.92 MHz 77.76 MHz input +5.3 1.5 ns 77.76 MHz output 38.88 MHz
-3.75 1.25 ns
-3.75 1.25 ns
51.84 MHz
-3.75 1.25 ns
77.76 MHz
-3.75 1.25 ns
155.52 MHz
-3.75 1.25 ns
F8527D_021IP_OPTiming_04
Revision 4.01/June 2006 (c) Semtech Corp.
Page 15
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Package Information
Figure 6 LQFP Package
FINAL
DATASHEET
Revision 4.01/June 2006 (c) Semtech Corp.
Page 16
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Thermal Conditions FINAL DATASHEET
The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Figure 7 Typical 64-Pin LQFP Package Landing Pattern
Revision 4.01/June 2006 (c) Semtech Corp.
Page 17
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Application Information
Figure 8 Simplified Application Schematic
FINAL
DATASHEET
VDD3 P1 5v 0v term_connect (+) C2 100uF C3 100nF EZ1086-3.3V ( C4 10uF_TANT +) C5 100nF AGND ZD1 BZV90C-5.6v DGND DGND2 DGND3 VDD5v VDD IC2
VOUT
3 VIN 1 GND
2
VDD2 VDDA
O2 An example setup where input and output clocks are hard wired to accept 19.44MHz on SEC1 and SEC2. T4e1out-ut21/re1con7 .5ured as: O1 -> 155.52MHz O2 -> 38.88MHz VDDA DGND C15 100nF AGND VDD C-MAC E2747_ 12.8MHz
DGND C14 100nF VDD
49 TCK 50 TDO 51 TDI 52 IC10 53 DGND6 54 VDD3 55 NC2 56 O2 57 VA3+ 58 AGND4 59 NC3 60 IC11 61 IC12 62 IC13 63 O1_FREQ2 64 SONSDHB
PORB C13 1nF DGND VDD
8 NC NC
R5 10K
7 NC
6
9 VS
NC
DGND
X1
3 NC
10 GNDb 1
OP 5 GND 4
DGND
AGND R1 C6 10R 100nF
VDD3 VDDA C7 100nF
Typical 12.8MHz oscillator
source failure indication R2 10R
DGND3 C8 100nF AGND
source switch control
17 FrSync 18 MFrSync 19 O1POS 20 O1NEG 21 GND_DIFF 22 VDD_DIFF 23 IC3 24 IC4 25 IC5 26 IC6 27 VDD5V 28 IP_FREQ0 29 SEC1 30 SEC2 31 DGND4 32 VDD1
1 AGND1 2 IC1 3 AGND2 4 VA1+ 5 LOS_ALARM 6 REFCLK 7 DGND1 8 VD1+ 9 VD2+ 10 DGND2 11 DGND3 12 VD3+ 13 SRCSW 14 VA2+ 15 AGND3 16 IC2
IC1 ACS8527
PORB 48 IC9 47 O1_FREQ1 46 O1_FREQ0 45 NC1 44 IC8 43 IC7 42 TMS 41 DGND5 40 VDD2 39 O2_FREQ1 38 TRST 37 O2_FREQ2 36 O2_FREQ0 35 IP_FREQ2 34 IP_FREQ1 33
NC
2
C12 VDD DGND
100nF
VDD5v
VDD
VDD R3 1M BSH205 M1
VDD
C10 100nF DGND optional only needed for 5v protection R4
C11 100nF DGND
PORB C16 220nF DGND
VDD2 FrSync MFrSync DGND2 O1P O1N
1K
C9 100nF DGND2
SEC1
SEC2
DGND
Optional circuit to ensure SRCSW is high on power-up
F8527D_031SimpleApp_01
Revision 4.01/June 2006 (c) Semtech Corp.
Page 18
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Abbreviations
APLL DPLL DS1 E1 I/O LOS LQFP LVDS PDH PLL POR ppm p-p rms RoHS SDH SEC SETS SONET SSU STM TCXO UI WEEE XO
FINAL References
DATASHEET
Analogue Phase Locked Loop Digital Phase Locked Loop 1544 kbit/s interface rate 2048 kbit/s interface rate Input - Output Loss Of Signal Low profile Quad Flat Pack Low Voltage Differential Signal Plesiochronous Digital Hierarchy Phase Locked Loop Power-On Reset parts per million peak-to-peak root-mean-square Restrictive Use of Certain Hazardous Substances (directive) Synchronous Digital Hierarchy SDH/SONET Equipment Clock Synchronous Equipment Timing source Synchronous Optical Network Synchronization Supply Unit Synchronous Transport Module Temperature Compensated Crystal Oscillator Unit Interval Waste Electrical and Electronic Equipment (directive) Crystal Oscillator
[1] AT & T 62411 (12/1990) ACCUNET(R) T1.5 Service description and Interface Specification [2] ETSI ETS 300 462-3, (01/1997) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 3: The control of jitter and wander within synchronization networks [3] ETSI ETS 300 462-5 (09/1996) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 5: Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment [4] IEEE 1149.1 (1990) Standard Test Access Port and Boundary-Scan Architecture [5] ITU-T G.736 (03/1993) Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s [6] ITU-T G.742 (1988) Second order digital multiplex equipment operating at 8448 kbit/s, and using positive justification [7] ITU-T G.812 (06/1998) Timing requirements of slave clocks suitable for use as node clocks in synchronization networks [8] ITU-T G.813 (08/1996) Timing characteristics of SDH equipment slave clocks (SEC) [9] ITU-T G.824 (03/2000) The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy [10] ITU-T K.41 (05/1998) Resistability of internal interfaces of telecommunication centres to surge overvoltages [11] Telcordia GR-253-CORE, Issue 3 (09/ 2000) Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria [12] Telcordia GR-499-CORE, Issue 2 (12/1998) Transport Systems Generic Requirements (TSGR) Common requirements [13] Telcordia GR-1244-CORE, Issue 2 (12/2000) Clocks for the Synchronized Network: Common Generic Criteria
Revision 4.01/June 2006 (c) Semtech Corp.
Page 19
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Trademark Acknowledgements
Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. ACCUNET(R) is a registered trademark of AT & T. C-MAC is a registered trademark of C-MAC MicroTechnology - a division of Solectron Corporation. ICT Flexacom is a registered trademark of ICT Electronics. Telcordia is a registered trademark of Telcordia Technologies.
FINAL Notes
DATASHEET
Revision 4.01/June 2006 (c) Semtech Corp.
Page 20
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Revision Status/History FINAL DATASHEET
design. The datasheet is only raised to FINAL status after the device has been fully characterized, and the datasheet content updated with measured, rather than simulated parameter values. This is a FINAL release (Revision 4.01) of the ACS8527 datasheet. Changes made for this document revision are given in Table 16, together with a summary of previous revisions. For specific changes between earlier revisions, refer (where available) to those earlier revisions. Always use the current version of the datasheet.
The Revision Status of the datasheet, as shown in the center of the datasheet header bar, may be DRAFT, PRELIMINARY, or FINAL, and refers to the status of the Device (not the datasheet) within the design cycle. DRAFT status is used when the design is being realized but is not yet physically available, and the datasheet content reflects the intention of the design. The datasheet is raised to PRELIMINARY status when initial prototype devices are physically available, and the datasheet content more accurately represents the realization of the Table 16 Revision History
Revision 2.00/ December 2002 3.00/April 2003 4.00/September 2003 All pages All pages All pages Table 3, Table 5, Table 6, Table 11, Table 12 and Figure 5. "Fast Activity Monitor" on page 8, "Status Reporting" on page 9, "Revision Status/History" on page 21. "ESD Protection" on page 10, "Latchup Protection" on page 10. 4.01/June 2006 Front and back pages and "Abbreviations" on page 19. "Trademark Acknowledgements" on page 20 and "Revision Status/History" on page 21. Back page "Over-voltage Protection" on page 10 Figure 6, Figure 7. Reference
Description of changes First full release. Major revision. First Release at FINAL status. Major revision. All pages reformatted. General update of cross-references. Tables and Figures updated. Sections updated.
New Sections inserted. Interim update to reflect availability of lead(Pb)-free packaged part and change to Semtech US address. Minor non-technical changes.
Taiwan address changed Hyperlink to Semtech website added. Updated Package diagram and footprint diagram. Former Tables 16 and 17 removed.
Revision 4.01/June 2006 (c) Semtech Corp.
Page 21
www.semtech.com
ACS8527 MUXPLL
ADVANCED COMMUNICATIONS Ordering Information
Table 17 Parts List
Part Number ACS8527 ACS8527T Description MUXPLL Line Card Protection Switch for PDH, SONET or SDH Systems Lead (Pb)-free package version of ACS8527; RoHS and WEEE compliant.
FINAL
DATASHEET
Disclaimers
Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User's implementation and design practices. It is the responsibility of the User to ensure equipment using this device is compliant to any relevant standards.
Contacts
For Additional Information, contact the following: Semtech Corporation Advanced Communications Products E-mail: Internet: USA: sales@semtech.com http://www.semtech.com 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 acsupport@semtech.com
FAR EAST: 12F, No. 89, Sec. 5, Nanking E. Road, Tapei, 105, TWN, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601
ISO9001
CERTIFIED
Revision 4.01/June 2006 (c) Semtech Corp.
Page 22
www.semtech.com

▲Up To Search▲

Price & Availability of ACS8527

	To Download ACS8527 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .